To identify the processing tolerance for the selective Cu chemical vapor deposition (Cu CVD) the processing windows were constructed with respect to deposition pressure and substrate temperature over thermally grown SiO2 vs. various conducting substrates of W, CoSi2, TiN, TiW, and Al. It is found that the width of selective deposition window decreases as the deposition pressure is increased, and no selective Cu deposition can be obtained as the deposition pressure exceeds 120 mTorr. The lowest temperatures for Cu CVD on various SiO2 substrates including thermally grown, BPSG, TEOS, and PECVD SiO2 were determined so that processing windows for selective Cu deposition on Variously patterned wafers can be constructed. The selective Cu deposition was also conducted on patterned substrates with submicrometer feature sizes using the PECVD SiO, as the interlayer dielectric. The nucleation of Cu on the SiO2 surface obviously acts as the major limitation for achieving selective Cu CVD. We postulate that the Cu containing adspecies, Cu(hfac), on the insulating SiO2 surface may combine by surface diffusion, and these assembled adspecies then disproportionate by exchanging electrons with each other rather than transferring electrons through the substrate.