Reduced metal contamination levels become ever more critical as ultralarge scale integrated device feature sizes shrink to less than or equal to 0.25 mu m Wafers may be contaminated with metals during their manufacture, but metals are more likely to be introduced at the wafer surface during integrated circuit processing. During high-temperature processing steps, the surface contaminants diffuse rapidly into the wafer bulk. Because carrier lifetime and diffusion length are strongly affected by the presence of parts per trillion levels of electrically active metal-related defect centers in the bulk of the wafer, these properties can be used to detect the presence of metal contamination. Unfortunately, these techniques are sometimes misused and misinterpreted. The more common techniques, their benefits, and limitations on their interpretation are discussed. A unified taxonomy to describe carrier lifetime characteristics is also proposed.