Copper decoration followed by transmission electron microscopy (TEM) observation is proposed for identifying defects in the buried oxides of silicon-on-insulator (SOI) substrates. This method comprises Si surface layer etching (i.e., exposure of the buried-oxide surface), oxide-defect location detection with copper decoration, and sample thinning for TEM observation and analysis. The advantage of copper decoration is that the electronic current needed for defect detection is very small, so the influence of the electronic current on the original oxide-defect structure can be minimized. Defects observed are categorized into four groups from the viewpoint of size and shape.