The use of chemical mechanical polishing (CMP) is rapidly increasing as a planarization technique in very large scale integrated process technology. Many of the planarizing applications have been directed toward interconnect dielectric planarization of triple level metal and quadruple level metal schemes. Interest in CMP as a tool for use in planarization of oxide-filled shallow trenches is now increasing. Isolation planarity with the silicon surface is required for achieving maximum linewidth control during subsequent silicon gate processing. Increased planarity also helps reduce the amount of overetch required during the polysilicon definition step especially that is required to clear minimum poly-to-poly spaces. Reactive ion etching overetch can contribute to junction leakage and critical dimension tolerance degradation. The utilization of CMP has been limited because of the dishing effect in wide field regions, as well as the difficulty of planarizing large and small features simultaneously. In this work, we discuss our shallow trench planarization technique, using chemical mechanical polishing alone. Dishing was reduced to less than 10 nm across 6 mm wide field regions. Large and small features were planarized simultaneously.