The predominant factors that contribute to the formation of polymer on the bottom and sidewalls of vias during plasma etching are discussed. Various cleaning techniques were tested and electrically verified to produce "clean" via holes for multilayer interconnect processes. We also examine how photoresist stripping conditions may impact via resistance. To achieve low contact resistance (<1 Omega/via) for submicron via holes. the removal of the sidewall and bottom polymer created during the reactive ion etch process is the most important factor.