This paper describes the fabrication process for an interconnect technology in silicon systems. The process involves the electroplating of chemically etched through-holes in silicon substrates. These plated holes act as vias between the front and back sides of the substrate. This method can be used in high-density multilayer three-dimensional systems to minimize the delay times between chips. It can also be used in the packaging of silicon sensors to address the problem of system partitioning. We report via resistance in the order of m Omega, isolation resistance between 1 to 3 G Omega, and capacitance less than 10 pF.