Silicon-on-insulator (SOI) structures comprised of fully dielectrically isolated device wells have been fabricated, utilizing a trench-before-bond process to create polish stops. The SOI layers have thicknesses between 1.5 and 3.0 mu m with uniformities of +/-5% across a 500 mu m device well, which would not be achievable with grind and polish techniques only. The SOI layer thickness was defined by the depth of isolation trenches, formed prior to bonding, which acted as the final SOI polish stops. The prebend planarization process is very dependent on polish conditions used. It was found that opting for a polishing slurry with a lower pH value allowed the planarization of polysilicon layers. The polish process resulted in refill layers that could be bonded without pattern-related voids. A similar polishing process also displayed minimal dishing in the final SOI device wells, as the variability of the polishing process is limited by the polish stops. The trench-before-bond process minimizes the risk of oxidation-induced defects, arising from SOI isolation trenches, as these are refilled prior to bonding. It also offers a cheaper alternative to epitaxial growth on SIMOX substrates as a means of obtaining layers within this thickness range.