Above wafer topography of the substrate, such as wafer clamps, is known to impact adjacent feature profiles during plasma etching of microelectronic devices. The consequences of subwafer topography, such as electrostatic chucks and cooling channels, on feature profiles is less well characterized. To investigate these issues we have developed and integrated a plasma equipment model and a Monte Carlo feature profile model, and applied the integrated model to investigate polysilicon etching in an inductively coupled plasma reactor. We find that, when using low conductivity wafers, subwafer topography reduces the sheath potentials above the wafer which results in lower ion energies incident on the wafer. Etch rates sensitive to ion power are therefore also reduced. Due to the perturbation of the presheath and sheath, subwafer topography can also affect the angular distribution of the ion flux incident on the wafer which then results in asymmetric etch profiles. Superwafer structures perturb both the magnitude and angular distribution of the ion flux due to shadowing at the edge of the wafer. This leads to lower etch rates and asymmetric etch profiles. Inhibitor fluxes can be used to control the etch profile shape but only at relatively low magnitudes of those fluxes.