A multilayer electron beam resist process for asymmetric gate recess for field-effect transistors (FETs) in compound semiconductors is presented. With this process, it is possible to decrease the drain conductance while maintaining a large source conductance by recessing the highly doped cap of the FET structure to a greater extent in the direction of the drain. This can be accomplished with a single electron-beam exposure process followed by a single step development due to the different sensitivities of the resist layers. A weak sidelobe exposure on the drain side of the gate is also needed during the electron-beam exposure process. This resist process is designed to reduce the number of lithography steps and the critical alignment required in the conventional "double-gate recess" process. InAlAS/In0.7Ga0.3As modulation-doped field-effect transistors (MODFETs) fabricated using the new process were found to have gate-to-drain breakdown voltages of 8.5 V, which was a significant improvement over the 2.25 V gate-to-drain breakdown voltages of the MODFETs fabricated using a conventional symmetric T-gate process.