A new fabrication process for ultrasmall high-current-density metal-oxide-semiconductor transistors is proposed. The device fabrication is based on anisotropic wet etching of silicon using bonded and etched back silicon-on-insulator (BESOI) material and a self-adjusting polysilicon gate technology. The special feature in the design of the transistor is a small silicon wire with a triangular instead of a planar cross section connecting the source and drain areas. Applying a moderate voltage to the poly-gate, a high electric field is built up in the top of the triangle which increases the volume of the conducting channel below the gate. For normal operating conditions, the three-dimensional current flow allows smaller lateral dimensions of the device that offers higher integration. Because of the BESOI material, faster device performance is expected. The physical principle is discussed and the basic fabrication techniques are described. First electrical investigations of the transistors operating at room temperature are presented providing evidence that the current density is considerably higher than in planar transistors.