We report on the various strategies for integrating III-V semiconductors to very large scale integrated Si logic along with their strengths and limitations. We also detail the monolithic integration method involving direct epitaxial growth where several material science issues have arisen. They require fundamental investigation to further advance implementation. Those issues are (i) the need for a highly ordered array of bilayer steps as an initial Si surface condition for heteroepitaxy, (ii) lower Si oxide desorption temperature, e.g., via electron cyclotron resonance plasma treatments to preserve the bilayer step ordering, and (iii) thinner strain relief layers to reduce the III-V on Si topology mismatch.