The objective of this study was for it to serve as a guide for understanding high density plasma induced damage during wafer fabrication and etchback for device debug, electron-beam, and failure analysis. A study of electrical degradation of packaged and fully processed transistors that were functionally etched back was carried out. Two high density plasma technologies, electron cyclotron resonance (ECR) and inductively coupled plasma (ICP), from various vendors, were evaluated. Transconductance (got), threshold voltage (Vt), subthreshold slope, and gate leakage (Ig) were measured before and after the functional etch, Degradation took place even without polysilicon being directly exposed to the plasma. It was found that there is a strong correlation between the threshold voltage shift, and gate current shift, and they exhibit a bimodal relationship. The gate edge intensive transistor was most susceptible to degradation. The design of the etchers seemed to be the key factor rather than the choice of technology (ECR or ICP) with regard to transistor degradation. Gate oxide breakdown due to the charging of metal lines, caused by nonuniform electrical charging of the surface, adequately explains the observed transistor parameter shifts.