In submicron GaAs metal semiconductor field-effect transistors, the shift in the transconductance (g(m)) peak towards the high negative gate voltage end is often observed. Factors causing this abnormality were investigated. It is believed that if the surface potential and the Schottky barrier potential are of the same order of magnitude then there will be a strong probability that the peak g(m) value will appear at high negative gate voltages rather than near zero gate bias. It was shown that under these circumstances the drain current at low gate biases is not under the direct influence of gate depletion but rather is controlled by surface depletion in the gate-drain gap. At high negative gate voltages, depletion under the gate has the dominant effect on channel current, and the device exhibits an improved performance. Recessed gate technology is thought to be a solution to eliminate the surface state effects of a free drain-source surface. It was shown that a simple gate recess will not eliminate the possibility of g(m) compression and shift unless the Schottky barrier potential is greater than the free-surface potential.