A self-aligned process was developed to control the gate-tip spacing, gate diameter, tip sharpness, and tip protrusion of Si field emission devices (FEDs). Such control is needed for the fabrication of FEDs with low turn-on voltage and high emission current. Using the mask erosion technique, 2-mu m-tall Si emitter tips were initially etched in a Cl-2 plasma generated by an electron cyclotron resonance source. Plasma oxides with different thicknesses were grown on the Si emitters as a sacrificial layer which creates close spacing between gate and tips, as well as sharpens the tip when removed in wet etchant. Sharp emitters with 8 nm tip radius and 80 nm gate-tip spacing were formed using plasma oxidation. Polyimide was used as the insulator and Mo was sputtered to form the self-aligned gate. By changing the polyimide thickness, gate diameter ranging from 220 to 880 nm and tip apex position ranging from 320 nm below the gate (nonprotruding) to 930 nm above the gate (protruding) were demonstrated. Emission current from an array of 100 tips increased from 261 to 598 mu A when the tips radii were decreased from 67 to 8 nm by sharpening. By decreasing the gate-tip spacing from 500 to 193 nm, the gate turn-on voltage was reduced from 91 to 38 V. In addition, highest emission current was found to occur when the tip apex was positioned 70 nm above the gate level.