Chip designs, for both logic and memory, are becoming increasingly large and complex. It is not unusual for the postprocessing of these designs to be one of the biggest bottlenecks in the mask order processing pipeline. To address this bottleneck a parallel postprocessing system was developed. It was named P5 for practically perfect parallel postprocessor. This system is in use for production processing of designs to be written on IBM＇s EL4+ electron beam lithography tool located in the Advanced Mask Facility in Essex Junction, VT. In addition the system is being enhanced with the addition of hierarchical data handling capability. Early results of this enhancement work are presented in this article.