This article reports on the impact of interlayer dielectric (ILD) deposition and processing on the characteristics and reliability of n-channel metal-oxide-silicon held-effect transistors (n-MOSFETs). The TLD materials used were silicon dioxide prepared from tetra-ethyl-ortho-silane, fluorinated silicon oxides (FSOs), and low-kappa polymers. The ILDs were deposited by means of plasma enhanced chemical vapor deposition (PECVD), PECVD and high density plasma (HDP), and spin coating, respectively. The devices with 90 Angstrom gate oxide and 0.35 mu m channel lengths were sensitive to poly-Si gate definition etching steps with antenna ratio 5 and 70 K. To assess the degree of degradation, charge pumping (CP), gate-oxide integrity as well as transistor＇s parameters were measured after Fowler-Norheim (FN) stressing. It is found out that PECVD deposition of FSO resulted in the highest degradation to the MOSFETs, whereas spinning-on and processing polymer ILD yielded the best performing and the most reliable MOSFETs. It is also found that device degradation in wafers with FSO as ILD depends on the deposition method of FSO, and that this degradation bears a reverse charging-antenna correlation. It is argued that this correlation is caused by the interaction between fluorine and plasma-charging damage.