Elevated source drain (ESD) structure in deep submicron metal oxide semiconductor field effect transistors (MOSFETs) can help reduce parasitic series resistance and simultaneously achieve shallow contacting junctions to minimize short channel effects. A self-aligned ESD structure in conventional complimentary metal-oxide-semiconductor processing can be achieved using silicon selective epitaxial growth (SEG). A robust low thermal budget high quality SEG process using a commercial rapid thermal chemical vapor deposition reactor for ESD formation has been demonstrated. The preclean sequence prior to SEG is the key to achieve facet-free epitaxy. Low line-to-line leakage: confirms the high selectivity to nitride and oxide. The growth on exposed polysilicon (poly) gates leads to gate linewidth widening and lower Sate sheet resistance. ESD parametric data suggest that the well doping needs to be optimized to counter the slight increase in n + -p diode leakage. Capacitance-voltage simulations indicate that the gate to drain capacitance initially decreases and then increases with SEG thickness.