The substitution of deposited alternative Sate dielectrics for thermally grown SiO2 in aggressively scaled complementary metal-oxide-semiconductor devices requires separate and independent processing steps for (i) the oxidation of the Si substrate to form the Si-dielectric interface and (ii) the deposition of thin film dielectric. Ultrathin plasma-oxidized Si-SiO2 interface layers which contribute approximately 0.3-0.4 nm to the overall electrical oxide thickness have been integrated into devices with Si nitride, Si oxynitride, and Ta2O5 alternative dielectrics. This article proposes an analogy between (i) microscopically inhomogeneous bulk glass alloys such as GeSex with 1 < x <2, and (ii) interfaces included in these composite gate dielectric-semiconductor structures including, for examples, the Si-SiO2 and internal dielectric SiO2-Si3N4 interfaces. Scaling relationships for bond defect states applied initially to microscopically inhomogeneous glasses and thin films are applied here to interfaces in stacked gate dielectrics.