Copper interconnect structures are being evaluated for 0.25 mu m minimum feature size technology and below. This work focuses on fabrication of one- and two-level test structures with copper metallization and both oxide and polymer interlevel dielectrics to demonstrate the compatibility of unit processes being developed for future copper-based interconnects. Emphasis is placed on dual Damascene patterning and material and process compatibility with such patterning and the required barriers and passivation techniques required with copper. Future directions of this work are described in this invited review paper.