Analysis of the components of parasitic series resistance in ULSI devices shows that interfacial contact resistivities less than 10(-7) Ohm cm(2) will be required for sub 100-nm ULSI devices in order to stay on the historical performance trend. With dimensional scaling, the series resistance-width product decreases because channel lengths are scaled, while it increases in contacts because the contact length is decreased. Unless the contact resistivity is also reduced, the contact resistance ultimately becomes higher than the channel resistance, and no performance advantage will be obtained by making the device smaller. The challenge in meeting the contacting requirements in the 1997 National Technology Roadmap for Semiconductors is especially difficult in light of the desire to simultaneously contact both n(+) and p(+) junctions with a single material and given the trend towards lower processing temperatures, in which the equilibrium dopant electrical activity is lower. Several techniques, such as dielectric capping during junction annealing, are effective in reducing contact resistivity by maximizing interfacial dopant concentrations and minimizing contact barrier heights. Higher saturated drive currents, due to lowered parasitic series resistance, are observed in deep submicron devices made using silicides as diffusion sources (SADS); this technique eliminates the interfacial dopant segregation that is associated with conventional silicidation. The use of elevated source drains (ESD) also allows the use of thicker silicides while minimizing the consumption-induced increase in contact resistivity that normally accompanies silicidation; as a result, ESD devices give higher drive currents. The recrystallization of amorphous layers has been observed to result in non-equilibrium dopant activation which can be many times the equilibrium value. Finally, the use of heterojunction contacts using Si-Ge in the context of elevated source/drain devices presents another way to achieve lower contact resistance.