A review is given of the 300 K electron and hole mobilities in Si/SiGe heterostructures in the light of potential applications in CMOS technology. Particular emphasis is placed on p-channel structures where the gains are likely to be highest. Prospects for further enhancements in hole mobility and the growth procedures and layer configurations needed to achieve this are discussed. Recent work on heterointerface quality, limited area growth of strain-tuning virtual substrates and carrier mobility is also reported.