MOS gated devices performances are mainly dependent on the dielectric/semiconductor interface characteristics. We have evaluated the different performances of 6H-SiC N-MOSFET structure for testing the feasibility of power VDMOS. We have observed the influence of growing the gate oxide on an implanted region, resulting in a decrease of the effective channel mobility. This effect is maintained at high temperature. We have also checked the switching capability of the MOSFET. The difference in the on-state losses is also observed.