We introduce modeling and simulation of topography evolution during processes used in the fabrication of integrated circuits. After an overview, the presentation is divided into three major sections. In the first section, we consider thermal processes. The first process considered in this section is the chemical vapor deposition (CVD) of SiO2 from TEOS (tetraethoxysilane). We discuss the use of film profile information to help decide between, and to help refine, kinetic models. The second example deals with thin film flow of doped glasses for planarization applications, and demonstrates model calibration. The second major section demonstrates the state of topography simulation for plasma processes. We demonstrate the use of physically motivated models that require calibration using experimental data for a given set of operating conditions. We first consider the plasma-enhanced chemical vapor deposition (PECVD) of silicon dioxide from TEOS and oxygen mixtures (PETEOS). We then consider ionized physical vapor deposition (IPVD) of copper, incorporating results of new calculations on the interactions of gas phase-species with the surface. As the last example in this section, we discuss a reactive ion etch (RTE) model. The last major section presents four applications. First, programmed rate CVD is discussed in some detail, in order to demonstrate how feature scale modeling can be used in process development. Next, the RIE model is used to demonstrate aspect ratio-dependent etching, and to show how simulations can be used to develop engineering relationships. The third example shows how topography simulations can be used to aid process integration studies, and involves PETEOS, etching and reflow simulations. The fnal example uses the model for PETEOS to demonstrate the roles of '3d/2d' and '3d/3d' (transport dimensionality/surface dimensionality) topography simulators in 'virtual wafer fabs'.