The introduction of copper interconnects into integrated circuits has increased the use of dual damascene dielectric etch applications because copper films are difficult to plasma etch. Fencing and faceting around the via hole during the trench etch of the via-first dual damascene integration scheme are particularly detrimental and can lead to problems during copper metallization and ultimately to device failure. Therefore, it is imperative that the evolution of these features be understood so that they can be avoided. In this article we will begin with an over-view of the via-first dual damascene integration scheme. Experimental results will then be presented that indicate the evolution of these features is heavily dependent upon the existing via profile and whether bottom antireflection coating and/or photoresist is in the via hole prior to starting the trench etch. An empirical model for fence formation was then confirmed by a simple profile simulator written in Visual Basic. Finally, several options for avoiding the evolution of fencing and faceting during the trench etch will be proposed.