We present the experimental details for the preparation of an ultrashort channel metal-oxide-semiconductor field-effect transistor (MOSFET) using a V-groove approach. This new fabrication process allows a definition of the channel with a resolution that exceeds the limit of the lithography used. The approach is based on the combination of electron beam lithography and anisotropic etching of an epitaxial silicon layered structure based on ultrathin silicon on insulator (SOI). A self-limiting etching process forms a "V" shaped groove into the silicon stack and the region at the tip of the V groove becomes the channel. The definition of the channel can be as small as 10 nm in length but it depends strongly on the anisotropic etching behavior, the quality of the molecular beam epitaxy grown layers, and the definition of the mask formed by the lithography. Here we discuss the fabrication of V-groove openings with the appropriate dimensions and quality required to fabricate nanoscale devices. The control of the V-groove process is discussed for making MOSFETs with good output characteristics.