The time evolution of a semiconductor wafer's feature-scale topography during chemical-mechanical polishing applied to copper films deposited over patterned dielectrics depends strongly on the bulk copper removal rate and the time at which copper clears from the up areas in the pattern. To first order, the overall evolution scales with the copper removal rate. But after the bulk copper is cleared locally, the evolution of the underlying dielectric and recessed copper depends strongly on the local clearing time. Complexities in analyzing the evolution data can be reduced by referencing that time. A new method of characterizing feature-scale planarization is described that removes the first-order clearing time and removal rate dependence from the topographical evolution graph. By doing this, the topographical evolution is understood in terms of initial topography and pad bending. The characterization is normally expected to be the same across the wafer, from die to die, and differences are attributed to nonuniform local pressures, pad condition, or other padwafer interface conditions, such as the local chemistry. Ideal cases and easily understood metrics named clearing offset, overpolish sensitivity, saturation level, and "clearing nonuniformity'' are introduced to provide a conceptual underpinning and utility of the method. The method is demonstrated using data measured on selected Cu structures in three different die locations during polishing on an Auriga polisher with Cabot 5001 slurry. (C) 2003 The Electrochemical Society.