Small ground rule (< 0.175 μm), high aspect ratio (feature size to depth ratio >40) trenches in silicon are necessary to achieve required values of cell capacitance in the fabrication of charge-storage capacitors in dynamic random access memory devices. Etching of trenches suffers from a dynamic reactive ion etching (RIE) lag mechanism caused by constriction of trench openings during the etch process. Also, at high aspect ratios (accentuated by constriction of trench openings), reduced ion energy and etchant species flux to the trench bottom (etch front) results in slower etch rates leading to etch stop. This dynamic RIE lag effect and potential etch stop pose significant challenges towards obtaining deeper trenches. In this paper, two methods are proposed to minimize these problems. Short duration cleaning steps, predominantly etching in nature without any builtin deposition component, are used intermittently during the multistep etching sequence. Mask selectivity is preserved as these cleaning steps do not contribute significantly to the mask etch rate. The first method decreases the constriction of the trench opening by thinning the sidewall deposition, thus partially restoring the design dimension of the trench opening. The second method removes the etch-stop or blocking layer at the bottom of the trench without significantly contributing to sidewall thinning. These methods increase the differential etch rate of silicon at high aspect ratios, thereby help achieve the higher silicon depths required to meet the manufacturing process tool utilization targets. (C) 2003 The Electrochemical Society.