Dual damascene dielectric etch technology is emerging as a key enabler for advanced integration schemes. Early implementations of copper dual damascene processes favored the trench-first approach. This approach has now been largely superseded by the via-first scheme for technology nodes below 250 nm. Several etch issues typically arise when implementing either of these approaches. The via-first approach can lead to either via veils or excessive faceting problems when the trench is etched. The traditional trench-first approach requires long via overetches and very high selectivity to the underlayer so that allowance can be made for vias that are misaligned or placed outside the trenches. Trench-first lithography employing organic resists often requires patterning over nonplanar surfaces, which can result in narrow process windows. Both the via-first and trench-first approaches increasingly require etching the trench without a stop layer. This places exacting demands on etch uniformity, etch front control, and sidewall profile angle control. Control of these issues is enhanced when the etch mechanisms responsible for driving them are understood. These and other issues as well as the current understanding of the relevant mechanisms are discussed for implementing copper dual damascene structures in plasma enhanced chemical vapor deposition undoped silicate glass or fluorinated silicate glass oxide films. (C) 2003 American Vacuum Society.