We demonstrate complementary exposure of 70 nm system-on-a-chip (SoC) devices in electron projection lithography using Nikon's EB stepper, NSR-EB1A, and a high-performance Si stencil mask (4X) fabricated by HOYA. A gate level of the SoC device pattern data called Anaheim was processed for mask fabrication using a 10 PC-clustered hierarchical data processing system in which complementary splitting was executed by the M-Split developed by Selete and ISS. Data processing times and output data volumes of the complementary split and of proximity effect correction were all drastically reduced by using our hierarchical data processing method. We optimized stitching features to compensate for the critical dimension (CD) changes that can occur with stitching errors caused by complementary exposures. The complementary stitching accuracy obtained was better than 20 nm and the CD accuracy was better than 10 nm for 100 nm line and space patterns because of the use of stitching features. (C) 2003 American Vacuum Society.