The proximity effect correction (PEC) system to achieve the practical processing time and data volume for sub-65 nm design-rule system on chip (SoC) devices is improved. The lump method, which is the technique to process several subfields at a time, is used to reduce the processing time for PEC. The hierarchical data processing for PEC is also proposed to reduce the data volume. A PC cluster system has been used to reduce the processing time for PEC. For an actual 70 nm design-rule SoC device data, the processing time has been reduced from 7.8 h to 10.3 min and the data volume has been reduced from 12.4 to 2.6 GB by using the lump method, the hierarchical data processing, and a, ten PC cluster system. And, we have confirmed that the required critical dimension accuracy of +/-5% is achieved for the device data in the simulation. We have successfully fabricated a full-size 8 in. Si stencil mask using the data with our PEC system for an actual 70 nm design-rule SoC device. (C) 2003 American Vacuum Society.