A process technology for 0.16 mum embedded dynamic random access memory (DRAM) with gate length of 0.16 mum both in nmos and pmos, respectively, and DRAM cell size of 0.28 mum(2) is described. A major characteristic of this process is the integration of proven logic and DRAM cell process from stand-alone logic and DRAM device with minimum additional process steps, and thus enhance yield and reliability of fabricated device. The major features are dual gate oxides, triple gate electrodes, cobalt (Co) salicide in gate and junction except DRAM cell region, tungsten (W) interconnection for bit line and local interconnection, cylinder-type stack capacitor with NO insulator film, and multilayer metallization up to 5 metals. Saturation currents of nmos and pmos are 550 and 235 muA/mum, respectively, at 1.5 V operation. Newly developed process, so-called logic open etch module, which planarizes DRAM cell region before formation of active junction and salicidation, gives stable pmos operation and Co salicide resistance, and also makes void-free gap fill between adjacent word lines in DRAM cell. Low temperature oxidation at 700 degreesC in NO film which is used as dielectric film in stack capacitor is developed, and thus prevent degradation both in pmos transistor and Co salicide. (C) 2004 The Electrochemical Society.