The electrical effects of RCA standard clean 1 (SC1) prior to the second gate oxidation for dual gate oxide formation was investigated by splitting the SC1 cleaning time for a 256 Mbit mobile dynamic random access memory (DRAM) operating at 1.8 V. The etch rate with respect to the oxide by SC1 cleaning was approximately 1.6 Angstrom/min. The threshold voltage (V-tn) of the n-type metal-oxide-semiconductor field-effect transistor (nMOSFET) in the thin oxide region was shown to be a similar value with varying the SC1 time, while the absolute threshold voltage (\V-tp\) of the pMOSFET increased by 4%. In the thick oxide MOSFETs. V-tn decreased by 15%, while on the contrary, \V-tp\ increased by 7%. V-tn was found to be mainly dependent on the decreased gate oxide thickness due to the deep boron peak depth. However, \V-tp\ appeared to be more dependent on the decrease of surface boron concentration due to a shallow boron peak and also to the influence by the enhanced pocket implantation effect. Consequently, it is proposed that the SC1 cleaning time should be less than 300 s in order to retain the reliable electrical properties for both thin and thick gate oxide MOSFETs due to the drastic decrease of V-tn and breakdown voltage (BVd(ssn)) (C) 2004 The Electrochemical Society.