The effect of thermal stress on the electrical properties of ferroelectric/semiconductor structure was investigated when introducing Y2O3 film as a barrier layer in the structure. Two different thermal stress states could be obtained by fast (400 degreesC/min) or slow (30 degreesC/min) cooling of sputter-deposited Y2O3 films on silicon wafer from 800 degreesC. The formation of interfacial layer containing Y-Si-O and SiO2 layers while annealing could be characterized by using a spectroscopic ellipsometry. The introduction of strain-induced defects from thermal stress of the fast cooled sample showed a soft breakdown at low applying voltage. In the capacitance-voltage relation, a flat band voltage shift, hysteresis, and stretch-out phenomena were also observed. Nd2Ti2O7 was spin deposited using sol-gel procedure on the Y2O3/Si to form a metal-ferroelectric-insulator field effect transistor structured sample. These Nd2Ti2O7/y(2)O(3)/Si samples were also furnace-atmealed at 800 degreesC and cooled down to room temperature fast or slowly. One order lower value of leakage current, 1E-8 A/cm(2) was observed with these samples when comparing with the Y2O3/Si samples. A soft breakdown of the fast cooled sample seemed to have the same origin as the fast cooled Y2O3/Si sample, i.e., the strain-induced defects in the interfacial layer containing Y-Si-O and SiO2 phases. Hysteretic gaps of the Nd2Ti2O7/Y2O3/Si samples showed a possibility to be used as a memory window for ferroelectric gate. (C) 2004 Elsevier B.V. All rights reserved.