Polished vacancy rich material is used in high volume manufacturing of logic and memory devices. Inherent to the crystal pulling process of these materials are voids in the silicon crystal causing trench-based failure in dynamic random access memory (DRAM) chips. The number of failures per die was observed to grow with decreasing feature size. The purpose of the simulation model presented in this report is to quantify the number of these failures for future DRAM generations and thus to gain information about future material related requirements. (C) 2005 The Electrochemical Society.