A three step methodology for the development of gate dielectrics on Ill-V semiconductors including atomistic interface studies, oxide template formation, and dielectric stack manufacturing has been proposed. The third and final step encompasses the realization of high-kappa GdGa0.4-xO0.6/Ga2O3 dielectric stacks on GaAs. This article reports high-kappa stacked gate oxides with an oxide relative dielectric constant of 20.8 +/- 1, a breakdown field exceeding 4 MV/cm, leakage currents of congruent to 2 X 10(-8) A/cm(2) at an electric field of 1 MV/cm, and a broad minimum of interface state density D-it <= 2 X 10(11) cm(-2) eV(-1) on n-type GaAs suggesting a U-shaped D-it distribution. The proposed methodology can potentially be extended to high-kappa gate dielectric development on elemental semiconductors such as Si and Ge and wide band gap semiconductors such as GaN. (c) 2005 American Vacuum Society.