The replacement Of SiO2 by oxynitride or high-kappa materials as the gate dielectric in advanced Si complementary metal-oxide-silicon (CMOS) technology requires an investigation of the interface quality between the dielectric and the Si substrate for any candidate dielectric. An accurate, precise and convenient metrology for the characterization of the interface trap density (D-it) would be useful to evaluate the hardware, processes, and integration schemes for the formation of alternative gate dielectrics. In this article, we report the extraction of D-it near mid-gap by implementing a well-known conductance method from small-signal measurements of MOS impedance for oxynitrides with a range of physical thicknesses and nitrogen content. The MOS system measured in this work is not formed from the fabrication of a device, but through the use of an elastic metal gate metrology system where measurements are made on unpatterned films. The technique allows rapid, precise, and quantitative information on the interface quality for gate dielectric materials. (c) 2005 American Vacuum Society.