As semiconductor manufacturing moves to smaller geometries, the existing methodologies for verifying the manufacturability of a design are increasingly cumbersome. Current practice is to use geometric "design rules"-such as minimum spacing and width constraints-to identify design configurations that are not manufacturable or likely to reduce yield. One manufacturing property that is particularly difficult to capture accurately with geometric rules is the robustness of the layout configuration with respect to variation through the lithographic process window. The nonlinear characteristics of optical partial coherence effects, particularly strong in modern exposure systems with off-axis illumination, are currently incorporated into the design rules through an exhaustive empirical process. The resulting design rules can be overly conservative to insure complete problem pattern capture, and this may result in unnecessary restrictions on the design that reduce the layout density or interfere with circuit performance. In this article a process model that has been designed to identify process sensitive layout configurations is presented. The model is a spatial filter constructed to select the diffraction components that are most sensitive to focus variation. This defocus model then may be applied to a layout pattern to find features that suffer with lithography focus variation. In addition, the technique may be employed once the optical components of a manufacturing process have been developed. Current results show a good correlation between patterns highlighted using the defocus filter and patterns which will be sensitive to process variations during simulated manufacturing. It is believed that this methodology integrated into physical verification techniques will help to identify yield-limiting layout configurations. (c) 2005 American Vacuum Society.