We have studied the impact of several Si selective epitaxial growth (SEG) process on the agglomeration of ultra-thin, patterned silicon-on-insulator (SOI) layers. Through a careful analysis of the effects of the in situ H-2 bake temperature (that followed an ex situ "HF-last" wet cleaning) and of the silicon growth temperature on the SOI film quality, we have been able to develop a low-temperature SEG process that allows the growth of Si on patterned SOI layers as thin as 3.4 nm without any agglomeration or Si moat recess at the Si window/shallow trench isolation edges. This process consists of an in situ H, bake at 650 degrees C for 2min, followed by a ramping-up of the temperature to 750 degrees C, then some SEG of Si at 750 degrees C using a chlorinated chemistry (i.e. SiH2O2 + HCl). (c) 2005 Elsevier B.V. All rights reserved.