In this paper, we propose a new concept of thin SiGe virtual substrates in which the intermediate in situ annealing steps during graded SiGe layer growth play a key role. This annealing step increases misfit dislocation flow and relaxes the graded SiGe layer with a relaxation of 97.8%. Using thermally driven relaxation (TDR), it is possible to control the strain relief and the propagation of threading dislocations (TDs) to the top of buffer layers. In addition TDR, chemical mechanical polishing (CMP) helps to reduce surface roughness comparable to Si wafer. The regrowth of Si0.8Ge0.2 layer on the polished Si0.8Ge0.2 buffer was found to keep its surface roughness and TD density. Optimized 1 mu m thick Si0.8Ge0.2 buffer exhibited similar to 1 nm of surface roughness and threading dislocation density was less than 4 x 10(5)/cm(2). (c) 2005 The Electrochemical Society.