The degradation of poly-Si thin film transistors (TFTs) under self-heating stress was investigated via the capacitance between the source and the gate (C-GS), and that between the drain and the gate (C-GD). Consequently, the normalized C-GS and C-GD after stress positively shift 2 V for the gate voltage near flat band voltage. In addition, C-GS raises about 40% for the lower gate voltage, while C-GD raises only about 10%. With simulation results, it is found that the self-heating effect creates interface states near the source region and the deep states near drain, resulting in the different inclines of the of C-GS and C-GD curves.