Atomic layer deposition (ALD) is demonstrated to be effective for filling gaps as small as similar to 3 nm and aspect ratios greater than 10 with no void defects. Thus, it is a promising technique to enable the fabrication of complementary metal oxide semiconductor (CMOS) transistors using a "gate-dielectric-last" process to minimize thermal exposure of the high-kappa gate dielectric, in order to avoid issues such as gate Fermi-level pinning and increased leakage current density associated with oxygen vacancy formation and crystallization. (c) 2007 The Electrochemical Society.