An analytical model of the above-threshold voltage transconductance of large grain polycrystalline silicon thin-film transistors (TFTs) is presented. The devices were fabricated on 50 nm thick polysilicon films prepared by combined solid phase crystallization (SPC) of amorphous silicon and excimer laser annealing (ELA) at various energy densities. The structural properties of the polysilicon films were investigated by transmission electron microscopy. The transconductance model includes exponential band tails fur the grain boundary traps, the effect of polysilicon/SiO2 interface scattering and the channel depth variation with gate voltage. Based on this model, the transconductance dependence on gate bias is investigated in devices with different interface roughness. It is found that at low gate voltages, the: transconductance increases with the gate bias due to the grain boundary barrier lowering effect. The observed decrease of the transconductance at high gate biases is mainly related to the size of the interface roughness.