Parasitic capacitance and resistance limit the VLSI device performance. Hence, a circuit model is needed to treat these effects correctly. This article focuses on the circuit models for the overlap capacitance (C-gd.overlap) and the fringing capacitance (C-gd.fringe) of MOSFETs. Comparisons between the models and the device simulations are carried out for verification of the models. Also, a limitation of C-gd.fringe model for a future device miniaturization is found based on SIA Road Map. We propose a modified C-gd.fringe model. The effectiveness of the modified model is demonstrated using two circuits.