In this paper. for the first time, we demonstrate that incorporation of a shallow, lightly doped floating P-layer in the drift region of a high voltage CMOS/BiCMOS compatible, 500 V lateral insulated gate bipolar transistor can result in a significant improvement of its forward bias safe operating area. Detailed numerical calculations and analysis show that such an approach can enhance the on-state voltage handling capability without decreasing the breakdown voltage. The position of such a layer is shown to have a significant impact on the SOA performance of the device for the parameters considered.