The effects of flash EEPROM floating gate (FG) morphology on the generation and density of fast programming bits in a 2Mbit flash EEPROM array has been characterized. These fast programming bits exhibit identical subthreshold characteristics similar to that of a normal bit after UV erase, thus establishing that the initial charge stored on the FG of both fast and normal bit is the same. Experimental results clearly indicates that the fast programming phenomena result from an interaction of the programming process with the FG polysilicon microstructure. An in-depth experimentation previously reported, reveals that the FG poly deposition and doping processes are crucial for controlling the desired Fowler-Nordheim tunneling. A correlation is established between the fast bit density observed in the memory arrays, the FG polysilicon grain size and tunneling field enhancement factor mu (R-c). A compact model of the fast programming bit memory threshold voltage as a function of the effective FG polysilicon grain area factor G(eff), and tunneling held enhancement factor mu (R-c) has been developed for the first time.