The electric fields present in drain depletion region of poly-silicon thin film transistors (poly-Si TFTs) result in the enhancement of emission rate from the traps. An empirical relation between the field enhanced emission rate and electric field is proposed, which can be used to model the leakage current of poly-Si TFTs as a function of gate bias and temperature. The leakage current shows good agreement with the experimental data over wide range of temperature and gate bias. The model can be useful for circuit simulation.