The read access time is a major performance index for DRAM products, on which the bit line delay is a critical factor. This delay is comparable to and tightly coupled with gate delay of both storage cell and sense amplifier, hence has to be solved as an integrated single component. In this paper, a voltage waveform and delay model of DRAM bit line for read logic-0 and logic-1 operation was developed. The bit line is modeled as a distributed resistance-capacitance line, and was solved based on simplified current models in both linear and saturation regions simultaneously. Our model shows good agreement with both SPICE and numerical device solvers, for both step and ramp word line signals as well as various bit line precharged levels. The new model significantly reduces the computation time to less than 1/200 that SPICE simulation requires. (C) 2002 Published by Elsevier Science Ltd.