Ne electrostatic discharge (ESD) clamp devices for using in power-rail ESD clamp circuits with the substrate-triggered technique ire proposed to improve ESD level in a limited silicon area. The parasitic n-p-n and p-n-p bipolar junction transistors (BJTs) in the CMOS devices ire used to form the substrate-triggered devices Cor ESD protection. Four substrate-triggered de-ices are proposed and investigated in this work, which are named as the substrate-triggered lateral BJT, the substrate-triggered vertical BJT, the substrate-triggered double BJT and the double-triggered double BJT. An RC-based ESD-detection Circuit Is used to generate the triggering Current to turn on the proposed substrate-triggered devices. In order to trigger on the parasitic bipolar transistors more effectively, the symmetric multiple-cell square-type layout method is used to realize these substrate-triggered devices. The power-rail ESD clamp circuits, with such substrate-triggered devices have been fabricated in a 0.6-mum CMOS process. Experimental results have shown that the substrate-triggered device with double-BJT Structure can provide 200%, higher ESD robustness in per silicon area, as compared to the NMOS with the traditional gate-driven design, (C) 2002 Elsevier Science Ltd. All rights reserved.