A device scheme for designing sub-0.12 mum partially depleted silicon-on-insulator (SOI) n-MOSFET's has been examined with respect to the channel dopant profile. Significant different channel dopant distribution can be easily obtained while fabricating sub-0.12 mum devices in the partially depleted SOI substrate, due to the buried oxide layer. A shallow channel dopant profile formed by low-energy channel implantation is found to suffer from bulk punch-through leakage. With forming a retrograde channel profile by using higher channel implantation energy, the bulk punchthrough leakage can be suppressed, but the device driving capability is degraded while meeting an off-state leakage criterion. As a result, by simply using adequate channel implantation energy, a properly deep channel dopant profile can be formed to result in a better control of short channel effect and also retain driving capability. (C) 2002 Elsevier Science Ltd. All rights reserved.