A new gate capacitance extraction method from S-parameter measurements is proposed. The distributed nature of MOS transistor and the in-series substrate resistance and in-parallel gate conductance are taken into consideration in the gate capacitance extraction by using high-frequency S-parameter measurements. The error due to dissipation factor can be more effectively reduced by this method, compared to the conventional C-V measurements. Successful extraction of gate capacitance from test transistors with designed test pads has been demonstrated. (C) 2002 Elsevier Science Ltd. All rights reserved.